DESIGN OF CCM POWER FACTOR CORRECTION BOOST CONVERTER
In continuous conduction mode (CCM)
power factor correction circuits, the inductor current does not reach zero during most switching cycles. Many tutorials incorrectly state that it never reaches zero. In reality, the current of course reaches zero near input voltage zero crossing.
The main advantage of continuous mode boost is lower ∆iL
and lower peak to average ratio. This reduces conduction losses and requires smaller EMI filter. The main disadvantage
is hard reverse recovery of the free-wheeling diode. This process generates high-frequency noise in the range of tens of megahertz and increases switching losses. Continuous mode of operation is typically used in SMPS with power levels greater than 100W. To the left is a conceptual schematic and timing diagrams of CCM boost. Below we'll derive the main design equations and provide a quick calculator. Let's start with inductor volt-second balance:
Note that since the average current is continuously changing according to the input voltage, strictly speaking, volt-seconds across L are not exactly balanced. However, because normally, the switching frequency Fsw
is at least three orders of magnitude higher than mains frequency, we can neglect net current change over one switching cycle.
- duty cycle, then ton
=DT and toff
Substituting this into (1) we find:
From (2) we can derive current ripple:
/L = Vin(Vo-Vin)/L×Fsw
=1/T- switching frequency.
In the equations (1)-(3) Vin is instantaneous value of input voltage. It is varying continuously with AC phase angle Φ(t) according to the following equation:
Vin(Φ)=√2×Vrms×sinΦ, where Φ(t)=2π×f×t, f- line frequency.
It is easy to determine from (3) that at given Vrms, ∆iL
reaches maximum the peak of the input sine wave is equal to Vout/2.
The condition of continuous conduction mode is ∆iL
, where ILpk
- peak value of filtered line-frequency current (shown in blue in our diagram).
Assuming perfect power factor correction (PF=1.0):
= √2×Po/(Vrms×η) (4),
where Po- output power, η - efficiency in decimal. Therefore the inductance should be selected according to the following:
If Vin varies in a wide range, then ∆iL
reaches maximum at Vin_pk=Vo/2. On practice, the designers select ∆iL
<20...50% of Ipk, so L should be 2...5 times larger than the minimum value from (5).
Let's now calculate the currents in this circuit. These numbers can be used for components selection and for thermal design. For simplicity we will assume that L is sufficiently large so we can neglect ∆iL
. Since the switch (which is usually a FET) conducts only during the DT portion of the period T, its RMS current during one switching period is IQrms
(Φ)×√D(Φ). All quantities here vary with the phase angle Φ of input voltage. Substituting (2) and (4) into the above expression yields:
averaged over entire period of input AC is:
Note that although technically we should've integrated from 0 to 2π, the result would be the same- RMS value of IQrms
over first quarter of input sine wave is the same as over entire AC cycle. Substituting (6) into (7) and calculating the integral (7) we get:
The above value determines conduction losses in the FET.
The boost diode conducts during (1-D)T time. Therefore during each switching cycle Idiode_rms
(Φ)×√(1-D(Φ)). By considering the integral of Idiode_rms
(Φ) squared similar to (7), the RMS diode current can be calculated as follows:
The diode should selected to withstand the Vo and idrms
. Also note that when it turns off, its reverse recovery current causes significant switching losses and generate noise in the range 30 to 50 MHz. Therefore the diode should be selected with ultra fast soft switching characteristic.
Output capacitor is charging when the diode conducts and is discharging to the load when "Q" is ON. Assuming the load consumes fixed DC current Po/Vo, we can find the total capacitor current:
The capacitor current contains two components: twice line frequency and switching frequency:
The capacitor should be selected to handle Ic_2F_rms
. Its capacitance should be enough to provide required hold up time at a given load Po.
This online calculator will provide you with basic power relationship for the boost converter design. For an example of complete power stage design see this schematic
of 300W active PFC pre-regulator.